1. Field of the Invention
Generally, the present disclosure relates to integrated circuits, and, more particularly, to transistors comprising a semiconductor alloy embedded in their respective source/drain regions.
2. Description of the Related Art
Transistors are the dominant components in modern electronic devices. Currently, several hundred millions of transistors may be provided in presently available complex integrated circuits, such as microprocessors, CPUs, storage chips and the like. It is then crucial that the typical dimensions of the transistors included in an integrated circuit are as small as possible, so as to enable a high integration density.
One of the most widespread semiconductor fabrication technologies is the complementary metal-oxide-semiconductor (CMOS) technology, wherein complementary field effect transistors (FETs), i.e., P-channel FETs and N-channel FETs, are used for forming circuit elements, such as inverters and other logic gates, to design highly complex circuit assemblies.
Transistors are usually formed in active regions defined within a semiconductor layer supported by a substrate. Presently, the layer in which most integrated circuits are formed is made out of silicon, which may be provided in crystalline, polycrystalline or amorphous form. Other materials such as, for example, dopant atoms or ions may be introduced into the original semiconductor layer.
A MOS field effect transistor (MOSFET), or generally a FET, irrespective of whether an N-channel FET or a P-channel FET is considered, comprises a source and a drain region, highly doped with dopants of the same species. An inversely or weakly doped channel region is then arranged between the drain and the source regions. The conductivity of the channel region, i.e., the drive current capability of the conductive channel, may be controlled by a gate electrode formed in the vicinity of the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region depends on, among other things, the mobility of the charge carriers and the distance along the transistor width direction between the source and drain regions, which is also referred to as channel length. For example, by reducing the channel length, the channel resistivity decreases. Thus, an increased switching speed and higher drive current capabilities of a transistor may be achieved by decreasing the transistor channel length.
However, reduction of transistor channel length may not be pushed to extreme limits without incurring other problems. For example, the capacitance between the gate electrode and the channel decreases with decreasing channel length. A solution to this problem consists in the so-called high-k/metal gate (HKMG) technology, which has become the standard manufacturing technology for transistors with gate lengths less than about 50 nm. According to the HKMG manufacturing process flow, the insulating layer separating the gate electrode from the channel region is comprised of a high-k material. This is in contrast to the conventional oxide/polysilicon (poly/SiON) method, whereby the gate electrode insulating layer is typically comprised of an oxide, preferably silicon dioxide or silicon oxynitride in the case of silicon-based devices. By high-k material, it is here referred to a material with a dielectric constant “k” greater than 10.
One more approach developed in order to increase the charge carrier mobility in the channel region consists of generating a certain type of strain in the channel region, since the charge carrier mobility in silicon strongly depends on the strain conditions of the crystalline material. This approach may be conveniently used in conjunction with the HKMG technology or with the conventional poly/SiON method.
Strain has been extensively used in semiconductor manufacturing based on the experimental finding that a compressive strain component in the channel region of a P-channel transistor generally results in a superior mobility of holes, thereby increasing switching speed and drive current of P-channel transistors. Analogously, applying a tensile stress to the channel region of an N-channel transistor may likely cause an increase of the mobility of electrons in the channel region.
In silicon-based transistors, a semiconductor alloy with the same crystal structure as silicon but with a slightly greater or smaller lattice constant may be used for applying a desired amount of compressive or tensile stress in the channel region of a FET, respectively. For example, if a certain degree of compressive strain is to be applied to the channel region of a P-channel FET, a semiconductor alloy with a greater lattice constant than silicon (Si) may be used, such as a silicon/germanium (SiGe) alloy with a variable concentration of germanium (Ge). Symmetrically, a semiconductor alloy with a slightly smaller lattice constant than Si, such as silicon/carbon (SiC), may be used for applying a desired degree of tensile stress to the channel region of an N-channel FET.
In order to induce the desired level of stress in the transistor channel region, the appropriate semiconductor alloy is embedded in the active region at the ends of the channel region. For example, after forming the gate electrode, cavities may be formed in the active region, adjacent to the gate electrode structure and on opposite sides thereof. The cavities thus formed may then be filled with a layer of the semiconductor alloy, by epitaxially depositing the semiconductor alloy into the cavity. When epitaxially grown on the silicon material, the semiconductor alloy generally experiences an internal compressive or tensile strain, depending on the lattice mismatch with silicon. This strain may then induce a corresponding compressive or tensile strain component in the adjacent channel region. Consequently, a plurality of process strategies have been developed in the past in order to incorporate a highly strained semiconductor alloy material in the drain and source areas of a transistor. A semiconductor alloy layer, for example an SiGe alloy or an SiC alloy, used in the manner described above will be hereinafter referred to as an “embedded semiconductor alloy.”
Embedding a semiconductor alloy in the source/drain region of a FET usually entails drawbacks and inconveniences, mainly due to the epitaxial growth process of the semiconductor alloy layer in the cavity formed in the active region.
FIG. 1a shows a cross-section of a semiconductor structure 100 formed according to the method known from the prior art. The semiconductor structure 100 includes a first active region 110a formed in a semiconductor layer 110, which may be comprised of crystalline silicon or of any other appropriate semiconductor material, such as germanium, gallium arsenide, indium arsenide, any other III-V semiconductor or the like.
A second active region 110b has been formed in the semiconductor layer 110. The second active region 110b is separated from the first active region 110a by an isolation region 140. The isolation region 140 is comprised of a dielectric material. For example, the material making up the isolation region 140 may comprise silicon dioxide (SiO2).
The isolation region 140 may be, for example, formed as a shallow trench isolation (STI). Typically, the isolation region 140 is obtained by forming a trench in the semiconductor layer 110, which is subsequently filled with the desired dielectric material. The trench is formed by using an etching process. The etching process is normally carried out in the presence of a patterned mask, which leaves exposed the surface portions of the semiconductor layer 110 to be etched and screens all other surface portions from the etching. The mask is first deposited as a continuum layer on the surface of the semiconductor structure and then patterned, typically by means of optical lithography.
The semiconductor structure 100 includes a transistor 150 formed partly in and partly on top of the first active region 110a. A second transistor, not shown in FIG. 1a, might be formed partly in and partly on top of the second active region 110b. 
The transistor 150 includes a gate structure 160 formed on the surface of the active region 110a. The gate structure 160 may have been formed according to the HKMG technology, or may be a traditional poly/SiON gate. A spacer structure 163 may be conveniently formed on the sidewalls of the gate structure 160. The spacer structure 163 may protect sensitive materials included in the gate structure 160. Furthermore, the spacer structure 163 may be conveniently used as a mask during implantation or etching processes performed in the course of the device manufacturing flow after gate formation.
As shown in FIG. 1a, two cavities are formed in the first active region 110a on opposite sides of the gate structure 160. More specifically, a first cavity has been formed on the left-hand side of the gate 160 and a second cavity has been formed on the right-hand side of the gate 160. The second cavity is partially defined by a surface of the isolation region 140 exposing dielectric material.
The first and the second cavities of the first active region 110a are filled with a first and a second embedded semiconductor alloy layer 122a and 124a, respectively. The semiconductor alloy layers 122a and 124a have been epitaxially formed in the first and second cavity, respectively. The semiconductor alloy of layers 122a and 124a is preferably the same. For example, layers 122a and 124a may comprise an SiGe alloy if the transistor 150 is a P-channel FET. Alternatively, layers 122a and 124a may comprise an SiC alloy if the transistor 150 is an N-channel FET.
As shown in FIG. 1a, the embedded semiconductor alloy layer 124a grown in the second cavity exposes a non-flat, tilted surface to the outside. This is due to the fact that the growth rate of the semiconductor alloy layer 124a is different at different points of the second cavity. More specifically, the semiconductor alloy layer 124a grows faster in correspondence to portions of the second cavity exposing the semiconductor material of the semiconductor layer 110. The exposed semiconductor material acts as a seed for the epitaxial growth of the semiconductor alloy. On the other hand, the epitaxial growth of the semiconductor alloy on the portions of the surface exposing the dielectric material of the isolation region 140 is seriously hindered. This causes an extremely uneven growth of the semiconductor layer 124a in the second cavity, resulting in a curved upper surface. This problem is known as the “ski slope” defect.
In order to get around the ski slope problem, a manufacturing strategy called “tucking” has been developed. The idea behind the tucking strategy is shown in FIGS. 1a-1c. 
FIG. 1a shows that the semiconductor structure 100 comprises a second gate structure 160d, besides the first gate 160 formed on the surface of the first active area 110a. The second gate 160d will be hereinafter referred to as a “dummy gate.” The dummy gate 160d may conveniently have been formed during the same manufacturing stage used for forming the gate 160. Thus, the dummy gate 160d has an analogous structure to the gate 160 and typically comprises analogous or the same materials as the gate 160. For example, the dummy gate 160d also has a spacer structure 163d formed on its sidewalls, analogously to the gate 163.
The dummy gate 160d extends partly on the surface of the isolation region 140 and partly on the surface of the second active region 110b. More specifically, a portion of the gate 160d, or of the spacer structure 163d, is formed onto a surface portion of the second active region 110b lying in proximity to the interface with the isolation region 140. A portion 112 of the second active region 110b is thus screened by, or “tucked,” under the dummy gate 160d. 
The semiconductor structure 100 also includes a further embedded semiconductor alloy layer 122b epitaxially grown in a cavity formed in the second active region 110b. The semiconductor alloy constituting layer 122b might be the same as that constituting layers 122a and 124a or a different semiconductor alloy.
The cavities hosting the semiconductor alloy layers 122a, 124a and 122b shown in FIG. 1a are preferably formed in the course of the same etching process, which is carried out after forming the gate structures 160 and 160d. Thus, the tucked semiconductor material in portion 112 of the second active region 110b is unaffected by the etching process, since it is screened by the dummy gate 160d. Consequently, the cavity formed by the etching process in the second active region 110b and to be filled with the semiconductor alloy 122b is defined by a surface exclusively exposing the semiconductor material of the active region 110b. 
FIGS. 1b and 1c are top views of the same portion of the semiconductor structure 100 during consecutive stages of the manufacturing flow leading to the configuration shown in FIG. 1a. 
FIG. 1b shows the semiconductor structure 100 after the isolation region 140 has been formed in the semiconductor substrate 110. We assume that the surfaces of the semiconductor layer 110 and of the isolation region 140 define a common plane, identified as the horizontal xy-plane. The isolation region 140 is adjacent to the active region 110b, so that the isolation region 140 and the active region 110b share an interface 142 defined by the boundary surface between the two areas. According to the state of the art, the interface 142 is flat, so that it defines a vertical plane substantially perpendicular to the horizontal xy-plane.
FIG. 1c shows the portion of the semiconductor structure 100 during a subsequent manufacturing stage to that shown in FIG. 1b. A gate structure 160d has been formed on the surface of the semiconductor layer 110. The gate structure 160d could, for example, be the dummy gate 160d shown in FIG. 1a. The gate 160d shown in FIG. 1 c has a longitudinal axis parallel to the direction identified by the intersection of the interface 142 with the horizontal xy-plane. This direction is parallel to the y-axis in the figure. The gate structure 160d is partly formed on the surface of the isolation region 140. Furthermore, a portion of the gate 160d in proximity to its right-hand edge is formed on the active region, so that the semiconductor region 112 indicated with a dotted line is tucked under the gate 160d. 
An etching process is then carried out in order to form a cavity 132b in the active region 110b. As the tucked semiconductor portion 112 is screened by the gate structure 160d, this is not etched away by the etching process. Consequently, the surface defining cavity 132b only exposes the semiconductor material making up the active region, and not the dielectric material of the isolation region. When the cavity 132b is filled with an embedded semiconductor alloy 122b, the system looks as shown in FIG. 1a. 
FIGS. 1a-1c show examples of single-sided tucking, which does not entail significant technical challenges. However, the manufacturing process is extremely critical when double-sided tucking is to be achieved, i.e., using the same gate structure for simultaneously tucking respective portions of two neighboring active areas.
Some of the problems encountered when trying to achieve double-sided tucking are schematically illustrated in FIG. 1d, wherein the semiconductor structure 100 includes two neighboring active areas (not shown) formed on opposite sides of the isolation region 140. The gate structure 160 has been formed so as to simultaneously lie on the surface of the isolation region 140 and of the two active regions, so that the gate 160 tucks a portion 114 of the first active region and a portion 112 of the second active region. An etching process results in the formation of a cavity 134a in the first active region and a cavity 132b in the second active region.
In order for the gate structure 160 to be able to tuck a semiconductor layer portion included in both active regions, the distance between the active regions must be small enough. This requirement results in an upper bound on the thickness of the isolation region 140, i.e., on the distance between the interfaces 142 and 146 formed by the isolation region 140 with the first and the second active regions, respectively.
As the gate length shrinks, the thickness of the isolation region 140 is required to decrease accordingly. For example, considering that typical gate lengths may be as small as about 20 nm in the currently most advanced semiconductor manufacturing technologies, the thickness of the isolation region 140 should ideally be of a few nanometers and may by no means exceed an upper bound of about 10 nm. However, by making the isolation region 140 thinner and thinner, other problems arise, due, for example, to the limited precision of the optical lithography techniques used when forming the isolation region 140.
A likely effect of excessively shrinking the thickness of the isolation region 140 is shown in FIG. 1 d, with the formation of an overlapping or bridging area 116 connecting the first and the second active regions. The bridging areas 116 arise since the thickness of the isolation region 140 is too small to be able to be resolved by optical lithography. Bridging areas 116 are extremely undesirable, since they act as electrical short circuits between neighboring active areas, thereby likely leading to device failure.
A need then exists for an improved transistor manufacturing technique enabling double-sided tucking in transistors requiring a semiconductor alloy embedded in the source/drain regions. Specifically, the trend of semiconductor manufacturing technologies towards a progressive reduction of the transistor gate length calls for an improvement in the tucking strategies known from the prior art.